Design of Near-threshold CMOS and TG Based Adder Circuit for Computing Applications

In recent years, near threshold computing is gaining additional significance to attain least energy consumption. In this work, Dynamic Threshold MOS (DTMOS) and Gate Level Body Bias (GLBB) schemes are assessed in the context of Hybrid Full Adder (HFA) scheme which employs CMOS and Transmission Gate (TG) logic to operate in ultra low voltage (ULV) applications. The quality metrics - Power, Delay, Energy and Energy Delay Product (EDP) are evaluated and comparison has been carried out with C- CMOS full adder. The post layout simulation results examine that, the developed HFA with GLBB circuit achieves savings of more than 37% in delay, 14% in energy and 46% in Energy Delay Product when compared with conventional CMOS scheme and other equivalent functionality designs at low supply voltage (0.2V). The design is further extended to realize 16-bit adder with possible buffers at suitable stages; it is found that the design is working efficiently.