A wide frequency range delay-locked loop using multi-phase frequency detection technique

This paper presents a wide frequency range delay-locked loop implemented with a 0.35 mu m CMOS technology. which can overcome the limited frequency range and false lock problem of conventional delay locked loop (DLL). The proposed simple DLL architecture comprising frequency and phase detector has better process-portability. The implemented DLL covers frequency range from 10 MHz to 200 MHz, which is limited only by the characteristics of delay cell. The DLL consume, 19.8 mW and shows 13 ps rms jitter at 3.3 V 150 MHz condition.