A Surface Potential Model of Junction less Surrounding Gate(JLSG) MOSFhT

被引：0

作者：

Dhanaselvam, P. Suveetha ^{[1
]}

Balamurugan, N. B. ^{[2
]}

Ananthi, A. Nithya ^{[1
]}

机构：

[1] VCET, Dept ECE, Madurai, Tamil Nadu, India

[2] TCE, Dept ECE, Madurai, Tamil Nadu, India

来源：

2013 INTERNATIONAL CONFERENCE ON GREEN COMPUTING, COMMUNICATION AND CONSERVATION OF ENERGY (ICGCE) | 2013年

关键词：

Junctionless MOSFET; Surrounding gate MOSFET; Surface Potential; Short channel effects;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new surface potential model for junctionless surrounding gate MOSFET is developed. Junction less MOSFET is a device that has similar structure like conventional MOSFET, with a homogeneous doping polarity and a uniform doping concentration across the channel, source and drain. Junction less device is more advantageous than junction device in the way of diminishing the effect of short channel behaviour. It is a very simple device to design as it eliminates junction implantation and annealing. In this paper, surface potential is developed and it is analyzed for various parameters like oxide thickness,Drain bias and compared with the result of junction based surrounding gate MOSFET.

引用

页码：237 / 243

页数：7

共 6 条

[1] Al-Ashrafy M., 2011, 2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC), Riyadh, P1, DOI [DOI 10.1109/SIECPC.2011.5876905, 10.1109/SIECPC.2011.5876905]
[2] Calazan R. M., 2012, CIRC SYST LASCAS 201, P1
[3] *IEEE STAND BOARD, 1985, IEEE STAND BIN FLOAT
[4] Kennedy J., 1995, 1995 IEEE International Conference on Neural Networks Proceedings (Cat. No.95CH35828), P1942, DOI 10.1109/ICNN.1995.488968
[5] Muñoz DM, 2009, INT CONF INTELL SYST, P243, DOI 10.1109/ISDA.2009.107
[6] Ratnaweera A., 2004, IEEE T EVOLUTIONARY, V8

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