A low-power 17-GHz 256/257 dual-modulus prescaler fabricated in a 130-nm CMOS process

被引：0
作者：
Ding, Y [1 ]
Kenneth, KO [1 ]
机构：
[1] Univ Florida, Silicon Microwave Integrated & Syst Res Grp, Dept Elect & Comp Engn, Gainesville, FL 32603 USA
来源：
2005 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2005年
关键词：
dual modulus prescaler; CMOS; low power;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A divide-by 256/257 dual-modulus prescaler has been fabricated in a 130-nm CMOS process. The synchronous divide-by-4/5 divider uses source coupled logic (SCL) D flip-flops with a resistive load to achieve the 17.2-GHz maximum operating frequency at input power of 0dBm, The prescaler requires 4.3 mA current from a 1.5-V supply. This circuit has the highest operating frequency and the lowest power consumption reported to date among CMOS dual-modulus prescalers that can operate at 10 GHz or higher. The prescaler also works up to 15.8 GHz with a 1.2-V supply and draws 3-mA current.
引用
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页码：465 / 468
页数：4
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