A GA-based timing-driven placement technique

被引：0

作者：

Yoshikawa, M ^{[1
]}

Terai, H ^{[1
]}

机构：

[1] Ritsumeikan Univ, Dept VLSI Syst Design, Kyoto, Japan

来源：

ICCIMA 2005: SIXTH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND MULTIMEDIA APPLICATIONS, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Deep-Sub-Micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, timing constraint has become the dominant factor in the performance of VLSI This paper discusses a novel timing driven placement technique through Genetic Algorithm. The proposed algorithm has a two-level hierarchical structure consisting of outline placement and detail placement. For selection control, new objective functions are introduced for improving interconnect delay, power consumption and chip area. Experimental result shows improvement of 5.8% for interconnect delay, 0.1% for power consumption and 0.8% for chip area.

引用

页码：74 / 79

页数：6

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