A Low-power, Bootstrapped Sample and Hold Circuit with Extended Input Range for Analog-to-Digital Converters in CMOS 0.18 μm

In this paper, an input range extended sample and hold circuit is proposed. This input range extension is achieved through connecting the body of the transistor, which charges the bootstrap capacitor, to its source. This structure allows the sampling section to accept a higher input voltage. Also, the bootstrap capacitor value and transistors sizes are scaled down and power consumption is reduced. The proposed method maintains the overall performance of the sample and hold circuit in analogy to previously reported works while it increases the amplitude of the differential input signal up to 1.8 V in 0.18 mu m CMOS technology. The proposed circuit is simulated using 0.18 mu m standard CMOS technology. The sample and hold circuit reaches a peak signal-to-noise and distortion ratio (SNDR) of 64.9 dB for 99.4 MHz input signal with a full-scale differential voltage equal to 1.8 V.