40 Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to re-time the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 k Omega and a differential output swing of 520mV(pp) with BER < 10(-9) for input spanning from 430 mu A(pp) to 4mA(pp). The measured integrated input-referred noise is 3.3 mu A(rms). The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2(31) - 1 PRBS input, the recovered clock jitter is 0.7ps(rms) and 5.6ps(pp). The retimed data exhibits 13.3ps(pp) jitter with BER < 10(-9) Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.