Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme

被引:19
作者
Matsunaga, Shoun [1 ]
Natsui, Masanori [2 ]
Ikeda, Shoji [3 ]
Miura, Katsuya [3 ,4 ]
Endoh, Tetsuo [5 ]
Ohno, Hideo [3 ]
Hanyu, Takahiro [2 ]
机构
[1] Tohoku Univ, CSIS, Sendai, Miyagi 9808577, Japan
[2] Tohoku Univ, Lab Brainware Syst, Elect Commun Res Inst, Sendai, Miyagi 9808577, Japan
[3] Tohoku Univ, Lab Nanoelect & Spintron, Elect Commun Res Inst, Sendai, Miyagi 9808577, Japan
[4] Hitachi Adv Res Lab, Tokyo 1858601, Japan
[5] Tohoku Univ, Ctr Interdisciplinary Res, Sendai, Miyagi 9808578, Japan
基金
日本学术振兴会;
关键词
Memory architecture - Metals - Tunnel junctions - Oxide semiconductors - Semiconductor junctions - MOS devices - Semiconductor storage - Associative storage - Cells - Cytology;
D O I
10.1143/JJAP.50.063004
中图分类号
O59 [应用物理学];
学科分类号
摘要
A perpendicular magnetic tunnel junction (P-MTJ)-based one-transistor/one-resistor (1T-1R) binary content-addressable memory (CAM) is proposed for a high-density nonvolatile CAM. The proposed CAM cell performs an equality-search operation between an input bit and the corresponding stored bit by detecting the difference of a "cell resistance'', where the cell resistance is determined by the series connection of one metal-oxide-semiconductor (MOS) transistor and one P-MTJ device. This circuit structure makes it possible to implement a compact nonvolatile CAM cell circuit with 1.25 mu m(2) of a cell size in a 0.14 mu m complementary MOS (CMOS)/P-MTJ process. Moreover, the equality-search operation in a bit-serial fashion is used for great reduction of the activity rate in the proposed CAM cell array, since most of the mismatched words in the CAM are detected by just several higher bits of comparison results in the word circuits. By applying a bit-level fine-grained power gating scheme, a fabricated 64-bit x 128-word nonvolatile CAM achieves high density with maintaining low search energy under 3.1% of activity rate in the cell array. (C) 2011 The Japan Society of Applied Physics
引用
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页数:7
相关论文
共 27 条
  • [1] 90 nm TCAM cell design with leakage suppression technique
    Chang, Y-J.
    [J]. ELECTRONICS LETTERS, 2009, 45 (06) : 300 - 301
  • [2] Hamada M, 2007, PR IEEE COMP DESIGN, P382, DOI 10.1109/ICCD.2007.4601928
  • [3] Current-induced magnetization switching in MgO barrier magnetic tunnel junctions with CoFeB-based synthetic ferrimagnetic free layers
    Hayakawa, Jun
    Ikeda, Shoji
    Miura, Katsuya
    Yarnanouchi, Michihiko
    Lee, Young Min
    Sasaki, Ryutaro
    Ichimura, Masahiko
    Ito, Kenchi
    Kawahara, Takayuki
    Takemura, Riichiro
    Meguro, Toshiyasu
    Matsukura, Fumihiro
    Takahashi, Hiromasa
    Matsuoka, Hideyuki
    Ohno, Hideo
    [J]. IEEE TRANSACTIONS ON MAGNETICS, 2008, 44 (07) : 1962 - 1967
  • [4] Distributed data-retention power Gating techniques for column and row co-controlled embedded SRAM
    Hua, CH
    Cheng, TS
    Hwang, W
    [J]. 2005 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING - PROCEEDINGS, 2005, : 129 - 134
  • [5] Ikeda S, 2010, NAT MATER, V9, P721, DOI [10.1038/NMAT2804, 10.1038/nmat2804]
  • [6] Magnetic tunnel junctions for spintronic memories and beyond
    Ikeda, Shoji
    Hayakawa, Jun
    Lee, Young Min
    Matsukura, Futnihifo
    Ohno, Yuzo
    Hanyu, Takahiro
    Ohno, Hideo
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (05) : 991 - 1002
  • [7] A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing
    Ikenaga, T
    Ogura, T
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (04) : 536 - 544
  • [8] Kim Y.-D., 2006, IEEE INT SOL STAT CI, P587
  • [9] KIMURA H, 2004, P INT TECH C CIRC SY
  • [10] Kimura K., 2007, IEEE P 50 MIDW S CIR, P855