First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits

Recently, we have developed a novel vertical split-gate Flash (or vertical 2T NOR) architecture in a n-channel device. In this work, we further develop the p-channel device counterpart, and demonstrate 4 different electron and hole injection methods, including band-to-band tunneling-induced hot-electron (BBHE), +FN electron, source-side injection hot-hole (SSIH), and -FN hole injections. The split-gate Flash allows both over-erase and overprogram supported by the select-gate (SG) transistor. Bit-alterable operations are possible, thus providing very flexible and versatile memory operations. Various combinations of P/E cycling endurance are studied, and it is found that BBHE electron together with -FN hole injections produce the best match for endurance, while other combinations especially with SSIH induce more degradations. The advantages of this device are (1) Both nand p-channel Flash can be fabricated on the same wafer; (2) The Flash transistors enjoy high ON/OFF ratio > 7 orders, good for a re-configurable switch; (3) Large tunable Vt window of 6V. These advantages offer good potential of realizing functional memories, such as being used in a reconfigurable circuit, especially for the connection block in a field programmable array (FPAA or FPGA).