Phase Noise and Spur Performance Limits for Fractional-N Frequency Synthesizers

被引：0
作者：
Kennedy, Michael Peter [1 ,2 ,3 ]
Mo, Hongjia [1 ,2 ,3 ]
Donnelly, Yann [1 ,2 ,3 ]
机构：
[1] Univ Coll Cork, Sch Engn Elect & Elect Engn, Cork, Ireland
[2] Tyndall Natl Inst, Cork, Ireland
[3] Tyndall Natl Inst, Microelect Circuits Ctr Ireland, Cork, Ireland
来源：
2015 26TH IRISH SIGNALS AND SYSTEMS CONFERENCE (ISSC) | 2015年
关键词：
LOCKED LOOPS;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
The output phase noise of a fractional-N frequency synthesizer comprises two components: intrinsic noise in the controlled oscillator itself, and extrinsic noise caused by unwanted modulation at its control input. The extrinsic noise contains both stochastic and deterministic components. This paper considers strategies to minimize the extrinsic noise component by addressing deterministic nonlinear dynamical mechanisms.
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页数：6
相关论文
共 13 条
[1]  
Analog Devices, 2011, ADF4350 DAT SHEET
[2]  
[Anonymous], 2006, ALL DIGITAL FREQUENC
[3]  
Egan W., 2011, ADV FREQUENCY SYNTHE
[4]  
Egan WilliamF., 2000, FREQUENCY SYNTHESIS, V2nd
[5]   A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones [J].
Familier, Eythan ;
Venerus, Christian ;
Galton, Ian .
IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2013, 61 (17) :4270-4283
[6]  
Gardner FM, 2005, PHASELOCK TECHNIQUES, 3RD EDITION, P1, DOI 10.1002/0471732699
[7]   Analysis of charge-pump phase-locked loops [J].
Hanumolu, PK ;
Brownlee, M ;
Mayaram, K ;
Moon, UK .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (09) :1665-1674
[8]  
Kennedy M.P., 2014, NONLINEAR THEORY ITS, V5, P349
[9]   Design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy [J].
Kratyuk, Volodymyr ;
Hanumolu, Pavan Kumar ;
Moon, Un-Ku ;
Mayaram, Kartikeya .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (03) :247-251
[10]  
Muer B.D., 2003, CMOS FRACTIONAL N SY
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