Dynamically Reconfigurable Parallel Architecture Implementation of 2D Convolution for Image Processing over FPGA

2D Convolution is the most convenient method to analyze digital image and video processing and has a variety of digital image processing applications such as edge detection, image enhancement, image segmentation, smoothing or blurring an image and can be applied to video processing on the basis of frame by frame for motion detection. Though the computational complexity of 2D convolution is comparatively high as it demands high level parallelism both for product and addition operations, it can be implemented on real time embedded system applications such as Application-Specific Integrated circuit (ASIC) or Field Programmable Gate Array (FPGA). As the convolved image directly depends on the kernel, proposed architecture is suitable for any kernel of 3x3 size. The objective of this study is to implement and synthesize a FPGA base image processing system based on 2D convolution on the basis of microprocessor architecture Simple-as-Possible. This system was designed and simulated in Verilog Hardware Description Language (Verilog HDL) and synthesized on Virtex-5 FPGA. The result shows that, the proposed design has lesser number of blocks (look up tables & registers) than other architecture and low time delay. So that, the complexity of the proposed architecture is less and it can be used in image processing applications.