A two-level interleaving architecture for serial convolvers

被引:3
作者
Marino, F [1 ]
机构
[1] Politecn Bari, Fac Ingn, Dipartimento Elettrotecn & Elettron, Bari, Italy
关键词
bit serial ASICS; convolvers/correctors; pipelined architectures;
D O I
10.1109/78.757248
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this correspondence, se present a bit-serial architecture for convolving/correlating long numerical sequences by long filter functions. Because of its two-level interleaving structure, the proposed device does not require "wait cycles" between consecutive input samples. As a result, it achieves the highest possible throughput. Cascadability, fault tolerance, feasibility in VLSI technology, and computing performances are discussed and analyzed.
引用
收藏
页码:1481 / 1486
页数:6
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