PROPTEST: A property-based test generator for synchronous sequential circuits

被引：24

作者：

Guo, RF ^{[1
]}

Reddy, SM

Pomeranz, I

机构：

[1] Intel Corp, Diag Technol Dept, Hillsboro, OR 97124 USA

[2] Univ Iowa, Dept Elect & Comp Engn, Iowa City, IA 52242 USA

[3] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2003年 / 22卷 / 08期

关键词：

automatic test pattern generation (ATPG); sequential circuit; test compaction; test generation;

D O I：

10.1109/TCAD.2003.814953

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We describe a property-based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences that achieve high fault coverages at low computational complexity. These include the use of static test compaction, input vector holding with optimal numbers of hold cycles, input vector perturbation, and identification of subsequences that are useful in extending the test sequence. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures.

引用

页码：1080 / 1091

页数：12

共 36 条

[1]

AKERS SB, 1990, PROCEEDINGS : INTERNATIONAL TEST CONFERENCE 1990, P786, DOI 10.1109/TEST.1990.114096

[2]

BOSHINI M, 2000, P EUR TEST WORKSH MA, P187

[3]

CHEN WT, 1989, IEEE COMPUT, V22, P28

[4]

Cheng W.-T., 1988, Proceedings of the 1988 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '88 (Cat. No.88CH2643-5), P66, DOI 10.1109/ICCD.1988.25661

[5]

CHENG WT, 1989, P INT S CIRC SYST MA, P1938

[6] RT-level ITC'99 benchmarks and first ATPG results [J].

Corno, F ;

Reorda, MS ;

Squillero, G .

IEEE DESIGN & TEST OF COMPUTERS, 2000, 17 (03) :44-53

[7]

Giani R, 2000, PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), P159, DOI 10.1109/ATS.2000.893619

[8] On improving static test compaction for sequential circuits [J].

Guo, R ;

Pomeranz, I ;

Reddy, SM .

VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2001, :111-116

[9] On speeding-up vector restoration based static compaction of test sequences for sequential circuits [J].

Guo, RF ;

Pomeranz, I ;

Reddy, SM .

SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, :467-471

[10] Sequential circuit test generation using dynamic state traversal [J].

Hsiao, MS ;

Rudnick, EM ;

Patel, JH .

EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS, 1997, :22-28

← 1 2 3 4 →