Phase Locked Loop with DC-Offset Removal for Grid Synchronization

被引：0

作者：

Smadi, Issam A. ^{[1
]}

Issa, Mohammad Bany ^{[1
]}

机构：

[1] Jordan Univ Sci & Technol, Elect Engn Dept, Irbid 22110, Jordan

来源：

45TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2019) | 2019年

关键词：

DC-offset elimination; phase locked loop; small signal model;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper proposes an efficient and simple solution for grid synchronization adopting a phase angle correction in the conventional synchronous reference frame (SRF) phase locked loop (PLL) with its small single model and stability analysis. The proposed method is computationally simple and capable of DC-offset rejection and perfectly synchronizing with the grid. The proposed method is compared with another powerful PLL method showing promising results.

引用

页码：4669 / 4673

页数：5

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