Relocation-aware Floorplanning for Partially-Reconfigurable FPGA-based Systems

被引：2

作者：

Rabozzi, Marco ^{[1
]}

Cattaneo, Riccardo ^{[1
]}

Becker, Tobias ^{[2
]}

Luk, Wayne ^{[2
]}

Santambrogio, Marco D. ^{[1
]}

机构：

[1] Politecn Milan, Milan, Italy

[2] Imperial Coll, London, England

来源：

2015 IEEE 29TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS | 2015年

关键词：

D O I：

10.1109/IPDPSW.2015.52

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Within this paper we present a floorplanner for partially-reconfigurable FPGAs that allow the designer to consider bitstream relocation constraints during the design of the system. The presented approach is an extension of our previous work on floorplanning based on a Mixed-Integer Linear Programming (MILP) formulation, thus allowing the designer to optimize a set of different metrics within a user defined objective function while considering preferences related directly to relocation capabilities. Experimental results show that the presented approach is able to reserve multiple free areas for a reconfigurable region with a small impact on the solution cost in terms of wire length and size of the configuration data.

引用

页码：97 / 104

页数：8

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