Design of Single Precision Floating Point Arithmetic Logic Unit

被引：0
|
作者：
Singh, Nisha [1 ]
Dhanabal, R. [1 ]
机构：
[1] VIT Univ, Vellore 632014, Tamil Nadu, India
来源：
2018 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENERGY SYSTEMS (ICEES) | 2018年
关键词：
floating point number; FPU; overflow; underflow; exceptions; normalization; etc;
D O I：
暂无
中图分类号：
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号：
0807 ; 0820 ;
摘要：
Floating point numbers are used in many applications such as telecommunications, medical imagining, radar, etc. In top-down design approach, four arithmetic modules, addition, subtraction, multiplication and division are combined to form a floating point ALU unit. Each module is independent to each other. In this paper, the implementation of a floating point ALU is designed and simulated. This paper presents the design of a single precision floating point arithmetic logic unit. The operations are performed on 32-bit operands. The algorithms of addition, subtraction, division and multiplication are modeled in Verilog HDL using ModelSim and an efficient algorithm for addition and subtraction module is developed in order to reduce the no. of gates used. The RTL code is synthesized using Synopsys RTL complier for 180nm TSMC technology with proper constraints.
引用
收藏
页码：133 / 137
页数：5
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