Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET

被引:5
作者
Banerjee, Pritha [1 ]
Sarkar, Anup [2 ]
Sarkar, Subir Kumar [1 ]
机构
[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India
[2] Womens Polytech, Kolkata, India
来源
MICROELECTRONICS JOURNAL | 2017年 / 67卷
关键词
Short channel effects (SCEs); Silicon-on-insulator (SOI)/silicon-on-nothing (SON) MOSFET; Dual-material double gate (DMDG); Drain-induced barrier lowering (DIBL); Subthreshold swing; Hot Carrier Effect (HCE); ANALYTICAL-MODEL;
D O I
10.1016/j.mejo.2017.07.005
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects (SCEs). Two dimensional (2-D) Poisson's equation with proper boundary conditions has been solved considering the parabolic potential approximation. The model includes the calculations of threshold voltage, electric field and subthreshold swing. The impact of variation of the device parameters such as gate length ratios, gate metal work functions on the performance of the device has been examined and the results are compared to that of dual-material double gate (DMDG) Silicon-on-Insulator (SOI) MOSFETs. The calculated results obtained have been validated with the numerical simulation data obtained from ATLAS, a 2-D device simulator from SILVACO.
引用
收藏
页码:50 / 56
页数:7
相关论文
共 21 条
[1]   Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review [J].
Chaudhry, A ;
Kumar, MJ .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (01) :99-109
[2]   A new two-dimensional analytical model for short-channel symmetrical dual-material double-gate metal-oxide-semiconductor field effect transistors [J].
Chiang, Te-Kuang ;
Chen, Mei-Li .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (6A) :3283-3290
[3]  
Colinge JP, 2008, ROM J INF SCI TECH, V11, P3
[4]  
D'Agostino Fabio, 2000, INTRO VLSI DESIGN E
[5]  
Deb S., 2010, J ELECT DEVICES, V8, P300
[6]   Work Function Engineering With Linearly Graded Binary Metal Alloy Gate Electrode for Short-Channel SOI MOSFET [J].
Deb, Sanjoy ;
Singh, N. Basanta ;
Islam, Nurul ;
Sarkar, Subir Kumar .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2012, 11 (03) :472-478
[7]  
Emerging Research Devices, 2009, INT TECHN ROADM SEM
[8]   2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs [J].
Goel, Ekta ;
Kumar, Sanjay ;
Singh, Kunal ;
Singh, Balraj ;
Kumar, Mirgender ;
Jit, Satyabrata .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (03) :966-973
[9]  
Gupta Santosh Kumar, 2012, INT J ADV SCI TECHNO, V38
[10]   Dual-material gate (DMG) field effect transistor [J].
Long, W ;
Ou, HJ ;
Kuo, JM ;
Chin, KK .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (05) :865-870