Performance and area scaling of 6T SRAM using SOI MOSFET at 32nm node

SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To improve memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices technology, making SRAM more vulnerable for variations. This variations influence the stability of SRAM. This paper compare six transistors (6T) SOI Static random access memory (SRAM) stability in hold/standby, read and write mode with 6T bulk SRAM at 32nm node. The effect of supply voltage, transistor scaling, word line voltage, and temperature on SRAM stability is analysed. It can be seen from the reading that the performance and area of SRAM can be improve by using SOI, as SOI gives better stability than bulk SRAM at same process parameter. The Data Retention Voltage of SOI SRAM is 50 % small than Bulk SRAM, which mean SOI can operate on smaller voltage than bulk. At same cell ratio SOI gives better performance than bulk SRAM, hence area can be reduced by using SOI MOSFET.