Single-event upset and snapback in silicon-on-insulator devices and integrated circuits

被引：38

作者：

Dodd, PE ^{[1
]}

Shaneyfelt, MR ^{[1
]}

Walsh, DS ^{[1
]}

Schwank, JR ^{[1
]}

Hash, GL ^{[1
]}

Loemker, RA ^{[1
]}

Draper, BL ^{[1
]}

Winokur, PS ^{[1
]}

机构：

[1] Sandia Natl Labs, Albuquerque, NM 87185 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2000年 / 47卷 / 06期

关键词：

D O I：

10.1109/23.903749

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single- event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

引用

页码：2165 / 2174

页数：10

共 19 条

[1] CHARACTERIZATION OF BIPOLAR SNAPBACK AND BREAKDOWN VOLTAGE IN THIN-FILM SOI TRANSISTORS BY 2-DIMENSIONAL SIMULATION [J].