Implementation of an FPGA-Based Motor Control with Low Resource Utilization

This paper presents a design and an implementation of a motor speed control for a permanent magnet direct-current (PMDC) motor by using a Field Programmable Gate Array (FPGA). In this study; quadrature encoder block, speed calculation block, digital analog conversion (DAC) block, pulse width modulation (PWM) block and PI controller block were developed to control the motor using FPGA. The system was realized using Altera Cyclone V SE 5CSEMA4U23C6N. The lowest logic utilization was aimed in order to establish a system with low resource utilization which is critical for FPGA design. All system blocks were developed by using 59 out of 15,880 Adaptive Logic Module (ALMs). The logic utilization was used under the 1%. Motor PWM signal was generated at 48.8 kHz with 10-bit resolution. The control algorithm was experimentally tested to provide stable speed against varying input voltage. It was shown that satisfactory results can be obtained with minimum resource usage for high speed applications.