A systematic approach to profiling for hardware/software partitioning

被引：5
|
作者：
Finc, M [1 ]
Zemva, A [1 ]
机构：
[1] Univ Ljubljana, Fac Elect Engn, Lab Integrated Circuits Design, Ljubljana 1000, Slovenia
来源：
COMPUTERS & ELECTRICAL ENGINEERING | 2005年 / 31卷 / 02期
关键词：
hardware/software (HW/SW) co-design; HW/SW partitioning; Field Programmable gate array (FPGA); embedded soft-core processor; performance analysis; profiling; system-on-programmable-chip (SoPC);
D O I：
10.1016/j.compeleceng.2004.07.003
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present an efficient approach to profiling for HW/SW partitioning. The execution of arbitrary SW code regions is analyzed with a clock-cycle accuracy without introducing an additional profiling induced performance overhead. Based on the profiling principle, performance analysis of the initial functional SW description and performance estimation of various HW/SW partitioning configurations are systematically and iteratively carried out. For an efficient evaluation of different partitioning possibilities no design and implementation of HW co-processing blocks are necessary. The principle equally covers the simulation and implementation domains. The approach is highly suitable for embedded soft-core SoPC applications. In order to demonstrate its use, we developed a COMET Profiler tool. The design flow is illustrated with two case studies. (c) 2005 Elsevier Ltd. All rights reserved.
引用
收藏
页码：93 / 111
页数：19
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