A high-speed residue-to-binary converter for three-moduli (2k, 2k-1, 2k-1-1) RNS and a scheme for its VLSI implementation

被引：61
|
作者：
Wang, W [1 ]
Swamy, MNS
Ahmad, MO
Wang, Y
机构：
[1] Concordia Univ, Ctr Signal Proc & Commun, Dept Elect & Comp Engn, Montreal, PQ, Canada
[2] Univ Texas, Dept Comp Sci, Richardson, TX 75083 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2000年 / 47卷 / 12期
基金：
加拿大自然科学与工程研究理事会;
关键词：
Chinese remainder theorem; digital signal processing; residue number system; residue-to-binary converter; VLSI implementation;
D O I：
10.1109/82.899659
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a high-speed residue-to-binary converter for the moduli set (2(k), 2(k) - i, 2(k-1) - 1) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40% faster. Also, the time-complexity product is improved by 20%. Following the top-down very large scale integration design flow, the proposed converter is implemented in 0.5-micron CMOS technology. Based on this moduli set, layouts of the 8-, 16-, 32- and 64-bit residue-to-binary converters, which can be used in further residual number sg stem designs, are generated and simulation results obtained.
引用
收藏
页码：1576 / 1581
页数：6
相关论文
共 37 条
  • [1] Residue-to-binary arithmetic converter for the moduli set (2k, 2k-1, 2k-1-1)
    Hiasat, AA
    Abdel-Aty-Zohdy, HS
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (02): : 204 - 209
  • [2] Multiplier using RNS to binary converter for specific moduli (2k-1, 2k, 2k+l)
    Kim, WW
    Jang, SD
    Chun, HS
    COMPUTERS AND THEIR APPLICATIONS, 2000, : 190 - 193
  • [3] A Reverse Converter for Three-Moduli Set (2k, 2n-1, 2n+1), k < n
    Hiasat, Ahmad
    2019 IEEE JORDAN INTERNATIONAL JOINT CONFERENCE ON ELECTRICAL ENGINEERING AND INFORMATION TECHNOLOGY (JEEIT), 2019, : 548 - 553
  • [4] Residue-to-Binary Converter for the New RNS Moduli Set {22n-2, 2n-1, 2'1+1}
    Vassalos, Evangelos
    Bakalis, Dimitris
    2019 PANHELLENIC CONFERENCE ON ELECTRONICS AND TELECOMMUNICATIONS (PACET2019), 2019, : 22 - 25
  • [5] A New Scaler for the Expanded 4-Moduli Set {2k-1, 2k+1, 22k+1, 22k}
    Hiasat, Ahmad
    2020 11TH INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION SYSTEMS (ICICS), 2020, : 429 - 433
  • [6] Residue to binary converter for the extended four moduli set {2k, 2n−1, 2n+1, 2n+1+1} for n odd
    M V N Madhavi Latha
    Rashmi Ramesh Rachh
    P V Ananda Mohan
    Sādhanā, 48
  • [7] Residue to binary converter for the extended four moduli set {2k, 2n-1, 2n+1, 2n+1+1} for n odd
    Latha, M. V. N. Madhavi
    Rachh, Rashmi Ramesh
    Mohan, P. V. Ananda
    SADHANA-ACADEMY PROCEEDINGS IN ENGINEERING SCIENCES, 2023, 48 (02):
  • [8] Efficient VLSI design of residue-to-binary converter for the moduli set (2n, 2n+1-1, 2n-1)
    Lin, Su-Hon
    Sheu, Ming-Hwa
    Wang, Chao-Hsiang
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2008, E91D (07): : 2058 - 2060
  • [9] Design of Reverse Converters for General RNS Moduli Sets {2k, 2n-1, 2n+1, 2n+1-1} and {2k, 2n-1, 2n+1, 2n-1-1} (n even)
    Patronik, Piotr
    Piestrak, Stanislaw J.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (06) : 1687 - 1700
  • [10] An Efficient Residue-to-Binary Converter for the New Moduli Set {2n/2 ± 1, 22n+1, 2n+1}
    Siewobr, Hillary
    Gbolagade, Kazeem A.
    Cotofana, Sorin
    2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), 2014, : 508 - 511
1234