共 50 条
[21]
Delay analysis of an input buffered ATM switch under two different scheduling disciplines
[J].
IEEE 2000 TENCON PROCEEDINGS, VOLS I-III: INTELLIGENT SYSTEMS AND TECHNOLOGIES FOR THE NEW MILLENNIUM,
2000,
:B266-B270
[22]
ATM switch architecture modelling under uniform and bursty traffic.
[J].
IEEE GLOBECOM 1996 - CONFERENCE RECORD, VOLS 1-3: COMMUNICATIONS: THE KEY TO GLOBAL PROSPERITY,
1996,
:767-771
[23]
Buffer design of non-blocking ATM switch for bursty traffic
[J].
IEEE INMIC 2001: IEEE INTERNATIONAL MULTI TOPIC CONFERENCE 2001, PROCEEDINGS: TECHNOLOGY FOR THE 21ST CENTURY,
2001,
:78-81
[26]
Analytical analysis of ATM switches with multiple input queues with bursty traffic
[J].
GLOBECOM'99: SEAMLESS INTERCONNECTION FOR UNIVERSAL SERVICES, VOL 1-5,
1999,
:1222-1226
[27]
An efficient scheduling algorithm for input-queuing ATM switches
[J].
IEEE BSS'97 - 1997 2ND IEEE INTERNATONAL WORKSHOP ON BROADBAND SWITCHING SYSTEMS PROCEEDINGS: WORKSHOP THEME: "SWITCHING SYSTEMS FOR THE BROADBAND INTERNET AND FOR QOS ON DEMAND",
1997,
:148-154
[28]
PERFORMANCE STUDY OF AN ATM SELF-ROUTING MULTISTAGE SWITCH WITH BURSTY TRAFFIC - SIMULATION AND ANALYTIC APPROXIMATION
[J].
EUROPEAN TRANSACTIONS ON TELECOMMUNICATIONS,
1993, 4 (04)
:443-453
[29]
Performance study of an ATM self-routing multistage switch with bursty traffic: Simulation and analytic approaximation
[J].
European transactions on telecommunications and related technologies,
1993, 4 (04)
:443-453
[30]
Delay analysis for maximal scheduling in wireless networks with bursty traffic
[J].
27TH IEEE CONFERENCE ON COMPUTER COMMUNICATIONS (INFOCOM), VOLS 1-5,
2008,
:385-393