Record-low on-resistance for 0.35 μm based integrated XtreMOS™ transistors

被引：20

作者：

Moens, P. ^{[1
]}

Bauwens, F. ^{[1
]}

Desoete, B. ^{[1
]}

Baele, J. ^{[1
]}

Vershinin, K. ^{[2
]}

Ziad, H. ^{[1
]}

Narayanan, E. M. Shankara ^{[2
]}

Tack, M. ^{[1
]}

机构：

[1] AMI Semicond Belgium, Westerring 15, B-9700 Oudenaarde, Belgium

[2] De Montfort Univ, Engn Technol Res Ctr, Leicester LEI 9BH, Leics, England

来源：

PROCEEDINGS OF THE 19TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS | 2007年

关键词：

D O I：

10.1109/ISPSD.2007.4294931

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Experimental data are shown for integrated smart power transistors breaking the silicon limit at 100V. The performance is close to the much lower super-junction limit for the given device pitch. The device uses standard trench technology, and is implemented in a 0.35 mu m smart power process. Key steps to improve the device performance yielding a record performance of 30 mOhm*mm(2) for a V-bd of 94V, are highlighted in the paper.

引用

页码：57 / +

页数：2

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