Impact of Fin Height on Bias Temperature Instability of Memory Periphery FinFETs

Fin height dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high-kappa metal gate (HKMG) FinFETs transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related to a reduced role of the defective fin corners and/or top surface. PBTI results reveal a similar, albeit less severe, impact of fin height, suggesting an impact of fin height on the high-kappa layer, with again an increased defectivity at the fin corners and/or top surface, whose effective role is reduced in the case of taller fin.