Combinational and sequential mapping with priority cuts

被引：95

作者：

Mishchenko, Alan ^{[1
]}

Cho, Sungmin ^{[1
]}

Chatterjee, Satrajit ^{[1
]}

Brayton, Robert ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept EECS, Berkeley, CA 94720 USA

来源：

IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/ICCAD.2007.4397290

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

An algorithm for technology mapping of combinational and sequential logic networks is proposed and applied to mapping into K-input lookup-tables (K-LUTs). The new algorithm avoids the hurdle of computing all K-input cuts while preserving the quality of the results, in terms of area and depth The memory and runtime of the proposed algorithm are linear in circuit size and quite affordable even for large industrial designs. For example, computing a good quality 6-LUT mapping of an AIG with 1M nodes takes 150Mb of RAM and I minute on a typical laptop. An extension of the algorithm allows for sequential mapping, which searches the combined space of all possible mappings and retimings. This leads to an 18-22% improvement in depth with a 3-5% LUT count penalty, compared to combinational mapping followed by retiming.

引用

页码：354 / 361

页数：8

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