A technique for transparent fault injection and simulation in VHDL

被引：5
|
作者：
Zwolinski, M [1 ]
机构：
[1] Univ Southampton, Dept Elect & Comp Sci, Southampton SO17 1BJ, Hants, England
来源：
MICROELECTRONICS RELIABILITY | 2001年 / 41卷 / 06期
关键词：
D O I：
10.1016/S0026-2714(01)00039-7
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A technique is described for the automatic insertion of fault models into VHDL gate models, using shared Variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. This transparent fault modelling is illustrated using a netlist obtained from the synthesis of a VHDL RTL combinational logic circuit. A method for automatic sequential fault simulation is further demonstrated. (C) 2001 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：797 / 804
页数：8
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