A technique for transparent fault injection and simulation in VHDL

被引：5
|
作者：
Zwolinski, M [1 ]
机构：
[1] Univ Southampton, Dept Elect & Comp Sci, Southampton SO17 1BJ, Hants, England
来源：
MICROELECTRONICS RELIABILITY | 2001年 / 41卷 / 06期
关键词：
D O I：
10.1016/S0026-2714(01)00039-7
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A technique is described for the automatic insertion of fault models into VHDL gate models, using shared Variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. This transparent fault modelling is illustrated using a netlist obtained from the synthesis of a VHDL RTL combinational logic circuit. A method for automatic sequential fault simulation is further demonstrated. (C) 2001 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：797 / 804
页数：8
相关论文
共 50 条
  • [1] A fault injection technique for VHDL behavioral-level models
    DeLong, TA
    Johnson, BW
    Profeta, JA
    IEEE DESIGN & TEST OF COMPUTERS, 1996, 13 (04): : 24 - 33
  • [2] VHDL fault injection questioned
    Ghosh, S
    IEEE DESIGN & TEST OF COMPUTERS, 1997, 14 (02): : 2 - 2
  • [3] An automated fault injection technique based on VHDL syntax analysis and stratified sampling
    Sheng, Weiguang
    Xiao, Liyi
    Mao, Zhigang
    DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 587 - 591
  • [4] Fault injection in VHDL descriptions and emulation
    Leveugle, R
    IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, : 414 - 419
  • [5] Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment
    Amendola, AM
    Benso, A
    Corno, F
    Impagliazzo, L
    Marmo, P
    Prinetto, P
    Rebaudengo, M
    Reorda, MS
    EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS, 1996, : 536 - 541
  • [6] Analogue fault simulation in standard VHDL
    Bruls, E
    Verstraelen, M
    Zwemstra, T
    Meijer, P
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1996, 143 (06): : 380 - 385
  • [7] Fault simulation of behavioral VHDL model
    Stefanovic, J
    KNOWLEDGE-BASED SOFTWARE ENGINEERING, 1998, 48 : 303 - 306
  • [8] Fault injection for verifying testability at the VHDL level
    Seward, SR
    Lala, PK
    INTERNATIONAL TEST CONFERENCE 2003, PROCEEDINGS, 2003, : 131 - 137
  • [9] VHDL testability analysis based on fault clustering and implicit fault injection
    Bietti, FS
    Ferrandi, F
    Fummi, F
    Sciuto, D
    PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 237 - 242
  • [10] Circuit partitioning for distributed VHDL fault simulation
    Ryan, CA
    NINTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 1996, : 255 - 258
12345