High Speed VLSI Architecture Design Using FFT for 5G Communications

被引：0

作者：

Devi, P. Lakshmi ^{[1
]}

Malipatil, Somashekhar ^{[2
]}

Surekha, P. S. ^{[2
]}

机构：

[1] St Peeters Engn Coll A, Dept Elect & Commun Engn, Hyderabad, Telangana, India

[2] Malla Reddy Engn Coll & Management Sci, Dept Elect & Commun Engn, Medchal, Telangana, India

来源：

INVENTIVE COMPUTATION AND INFORMATION TECHNOLOGIES, ICICIT 2021 | 2022年 / 336卷

关键词：

Coordinate rotation digital computer (CORDIC); FFT; DFT; Xilinx ISE 14.7; Verilog; 5G; VLSI; PROCESSOR;

D O I：

10.1007/978-981-16-6723-7_22

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high speed FFT processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point DFTs for 5G, WLAN. The processor is designed for high speed applications and source code is written in Verilog. Synthesis and simulation is done in Xilinx ISE 14.7. The power dissipation is minimized (20.3 mW) and delay is 9.539 ns and further extension is done using CORDIC processor delay is 7.55 ns. In this paper, high speed VLSI Architecture designed using FFT for 5G Communications. The proposed results are compared with the existed work.

引用

页码：297 / 304

页数：8

共 50 条

[41] High-speed design for mixed radix FFT algorithm based on multi-bank memory strategy [J].

Ma, Cuimei ;

Wang, Yanfei .

IEICE ELECTRONICS EXPRESS, 2016, 13 (18)

[42] A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps [J].

Zhang, Ling ;

Yang, Jing ;

Shi, Cong ;

Lin, Yingcheng ;

He, Wei ;

Zhou, Xichuan ;

Yang, Xu ;

Liu, Liyuan ;

Wu, Nanjian .

SENSORS, 2021, 21 (18)

[43] Design of adaptive MC-CDMA receiver using low power parallel-pipelined FFT architecture [J].

Sivakumar, Senthil M. ;

Jayadhas, Arockia S. ;

Arputharaj, T. ;

Banupriya, M. .

2013 PAN AFRICAN INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE, COMPUTING AND TELECOMMUNICATIONS (PACT), 2013, :44-+

[44] A power-efficient variable-length prime factor MDC FFT architecture for high-speed wireless communication applications [J].

Chelliah, Antony Xavier Glittas Xavier ;

Robinson, Bibin Sam Paul Samuel ;

Sellathurai, Mathini ;

Gopalakrishnan, Lakshminarayanan .

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2020, 120

[45] Demonstration of a 47.8 GHz High-Speed FFT Processor Using Single-Flux-Quantum Technology [J].

Ke, Fei ;

Chen, Olivia ;

Wang, Yanzhi ;

Yoshikawa, Nobuyuki .

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2021, 31 (05)

[46] 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches [J].

Shih, Xin-Yu ;

Liu, Yue-Qu ;

Chou, Hong-Ru .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64 (06) :1456-1467

[47] Design, Simulation and FFT Analysis of Sense Amplifiers for DRAM Memories using C5 process for CMOS [J].

Johri, Swasti ;

Singh, Ojaswi ;

Johari, Ayoush .

2016 IEEE STUDENTS' CONFERENCE ON ELECTRICAL, ELECTRONICS AND COMPUTER SCIENCE (SCEECS), 2016,

[48] Using a Chaotic Digital System to Generate Random Numbers for Secure Communication on 5G Networks [J].

Alrikabi, Haider Th. Salim ;

Aljazaery, Ibtisam A. ;

Alaidi, Abdul Hadi Mohammed .

ENGINEERING TECHNOLOGY & APPLIED SCIENCE RESEARCH, 2024, 14 (02) :13598-13603

[49] Design Space Exploration of FFT Accelerators for IEEE 802.11ax Using High-Level Synthesis [J].

Lee, Uyong ;

Parks, Yeji ;

Heo, Junsu ;

Park, Sungkyung ;

Park, Chester Sungchung .

2024 IEEE 35TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, ASAP 2024, 2024, :120-121

[50] Design of High Speed, Reconfigurable Multiple ICs Tester using FPGA Platform [J].

Rabakavi, Basavaraj ;

Siddamal, Saroja .

2018 3RD INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT - 2018), 2018, :909-914

← 1 2 3 4 5 →