共 50 条
[21]
Nonlinear Binary Codes and Their Utilization for Test
[J].
2018 IEEE 21ST INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS),
2018,
:15-20
[22]
Scan latch design for delay test
[J].
ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY,
1997,
:446-453
[24]
Low power Test Pattern Generator for BIST
[J].
2015 SELECTED PROBLEMS OF ELECTRICAL ENGINEERING AND ELECTRONICS (WZEE),
2015,
[25]
Low Power Efficient Built in Self Test
[J].
2011 IEEE INTERNATIONAL CONFERENCE ON MICROWAVES, COMMUNICATIONS, ANTENNAS AND ELECTRONIC SYSTEMS (COMCAS 2011),
2011,
[26]
Low Power Compression of Incompatible Test Cubes
[J].
INTERNATIONAL TEST CONFERENCE 2010,
2010,
[27]
Test Power Optimization Using Clock Gating
[J].
2017 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING, INSTRUMENTATION AND CONTROL TECHNOLOGIES (ICICICT),
2017,
:12-16
[28]
A study on signature analyzer for design for test (DFT)
[J].
2004 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS,
2004,
:138-142
[29]
Embedded Test for Highly Accurate Defect Localization
[J].
2011 20TH ASIAN TEST SYMPOSIUM (ATS),
2011,
:213-218
[30]
Test Power Optimization Using Clock Gating
[J].
2017 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING, INSTRUMENTATION AND CONTROL TECHNOLOGIES (ICICICT),
2017,
:1079-1083