Properties of silicon-on-insulator structures and devices

The physical grounds for making SOI structures by the DeleCut (ion irradiated deleted oxide cut) method are considered. This method is a modification of the commonly known Smart Cut (R) technique and aims at eliminating the disadvantages of the basic method [1]. The proposed method makes it possible to considerably lower the annealing temperature and the content of radiation defects in SOI structures. It allows the thickness of a split-off Si layer and a transition layer between the SOI layer and a buried oxide to be reduced. The method also reduces the nonuniformity in the thickness of the SOI layer and the insulator to several nanometers. By using DeleCut, new SOI structures were formed on wafers with diameters as large as 150 mm; the structures included dislocation-free SOI layers of 0.003-1.7 mum in thickness and a buried thermal SiO2 oxide (0.05-0.5 mum). These structures have good electrical characteristics, which is supported by fabricating the submicrometer (0.2-0.5 mum) SOI-based CMOS transistors and test integrated circuits. (C) 2001 MAIK "Nauka/ Interperiodica".