Color counting and its application to path delay fault coverage

被引:4
|
作者
Deodhar, J [1 ]
Tragoudas, S [1 ]
机构
[1] Intel Corp, TDC, Austin, TX 78746 USA
关键词
D O I
10.1109/ISQED.2001.915259
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We propose a new technique for computing exact fault coverage for an? fault model. it consists of appropriate formation and counting of colors. Each color represents a set of faults, and the definition of colors varies according to the fault model. The technique utilizes the two aspects on which the fault coverage for any model depends, the circuit lines and the patterns applied to the circuit. Depending upon the sample space of faults for a given model, the representation of faults as colors differs. Colors are generated in a greedy and on demand manner ensuring they are unique. Even though the technique is simple in nature, it has never been used to calculate fault coverage for any fault model before. In this paper we apply ii to calculate the fault coverage for the path delay fault model. Our experimental results show improvement over the existent techniques for abovementioned model.
引用
收藏
页码:378 / 383
页数:6
相关论文
共 50 条
  • [31] Remote path delay fault simulation
    Gjermundnes, O
    Aas, EJ
    DSD 2005: 8TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2005, : 428 - 434
  • [32] Exact delay fault coverage in sequential logic under any delay fault model
    Kumar, Mahilchi Milir Vaseekar
    Tragoudas, Spyros
    Chakravarty, Sreejit
    Jayabharathi, Rathish
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (12) : 2954 - 2964
  • [33] Delay Fault Coverage Increasing in Digital Circuits
    Siebert, Miroslav
    Gramatova, Elena
    16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013), 2013, : 475 - 478
  • [34] Transition path delay faults: A new path delay fault model for small and large delay defects
    Pomeranz, Irith
    Reddy, Sudhakar M.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (01) : 98 - 107
  • [35] A flexible path selection procedure for path delay fault testing
    Pomeranz, I
    Reddy, SM
    17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 152 - 159
  • [36] Probabilistic model for path delay fault testing
    Su, Chih-Yuang
    Wu, Cheng-Wen
    2000, IIS, Taipei, Taiwan (16)
  • [37] Recursive Path Selection For Delay Fault Testing
    Chung, Jaeyong
    Abraham, Jacob A.
    2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2009, : 65 - 70
  • [38] Path delay fault simulation of sequential circuits
    Chakraborty, TJ
    Agrawal, VD
    Bushnell, ML
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (02) : 223 - 228
  • [39] SpeedGrade: An RTL path delay fault simulator
    Kim, KS
    Jayabharathi, R
    Carstens, C
    10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 239 - 243
  • [40] An adaptive path delay fault diagnosis methodology
    Padmanaban, S
    Tragoudas, S
    ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2004, : 491 - 496