Color counting and its application to path delay fault coverage

被引:4
|
作者
Deodhar, J [1 ]
Tragoudas, S [1 ]
机构
[1] Intel Corp, TDC, Austin, TX 78746 USA
关键词
D O I
10.1109/ISQED.2001.915259
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We propose a new technique for computing exact fault coverage for an? fault model. it consists of appropriate formation and counting of colors. Each color represents a set of faults, and the definition of colors varies according to the fault model. The technique utilizes the two aspects on which the fault coverage for any model depends, the circuit lines and the patterns applied to the circuit. Depending upon the sample space of faults for a given model, the representation of faults as colors differs. Colors are generated in a greedy and on demand manner ensuring they are unique. Even though the technique is simple in nature, it has never been used to calculate fault coverage for any fault model before. In this paper we apply ii to calculate the fault coverage for the path delay fault model. Our experimental results show improvement over the existent techniques for abovementioned model.
引用
收藏
页码:378 / 383
页数:6
相关论文
共 50 条
  • [21] Line coverage of path delay faults
    Majhi, AK
    Agrawal, VD
    Jacob, J
    Patnaik, LM
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (05) : 610 - 614
  • [22] On the fault coverage of gate delay fault detecting tests
    Pramanick, AK
    Reddy, SM
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (01) : 78 - 94
  • [23] Tutorial: Delay fault models and coverage
    Majhi, AK
    Agrawal, VD
    ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 364 - 369
  • [24] On the fault coverage of gate delay fault detecting tests
    Nextwave Design Automation Inc, San Jose, United States
    IEEE Trans Comput Aided Des Integr Circuits Syst, 1 (78-94):
  • [25] AN EFFICIENT NONENUMERATIVE METHOD TO ESTIMATE THE PATH DELAY-FAULT COVERAGE IN COMBINATIONAL-CIRCUITS
    POMERANZ, I
    REDDY, SM
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (02) : 240 - 250
  • [26] Improving path delay fault testability by path removal
    Sparmann, U
    Koller, L
    16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1998, : 200 - 208
  • [27] Path Unselection for Path Delay Fault Test Generation
    Pomeranz, Irith
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (02) : 267 - 275
  • [28] Path Delay Fault Diagnosis Using Path Scoring
    Lim, Yoseop
    Lee, Joohwan
    Kang, Sungho
    ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 638 - 641
  • [29] Primitive path delay fault identification
    Sivaraman, M
    Strojwas, AJ
    TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 95 - 100
  • [30] Path delay fault testability analysis
    Sosnowski, J
    Wabia, T
    Bech, T
    IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, : 338 - 346