Scaling embedded EEPROMs for the integration in deep submicron technologies

被引：0
|
作者：
Duffy, R [1 ]
Concannon, A [1 ]
Mathewson, A [1 ]
Lane, B [1 ]
机构：
[1] Natl Univ Ireland Univ Coll Cork, Natl Microelect Res Ctr, Cork, Ireland
来源：
MICROELECTRONICS JOURNAL | 2001年 / 32卷 / 01期
关键词：
embedded nonvolatile memory; submicron geometries; scaling issues; short channel effects; disturbs;
D O I：
10.1016/S0026-2692(00)00074-4
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Applications such as systems-on-chip and memory cards require embedded code storage at increasingly small dimensions. In this work a study of scaling embedded EEPROM cells for the integration in deep submicron technologies is undertaken. A well-structured methodology will be proposed and applied to a number of different EEPROM cell types that have been integrated successfully in submicron CMOS processes to date. When scaling embedded nonvolatile memories it is difficult to generate accurate scaling laws or general rules because the performance targets and operating requirements of the memory cells are strongly dependent on the application and process technology in which they are to be integrated. It is possible to generate rules that are application or process technology specific, but it is the aim here to evaluate the scaling of these embedded EEPROMs without a particular application or process technology in mind. (C) 2000 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：35 / 42
页数：8
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