Scaling embedded EEPROMs for the integration in deep submicron technologies

被引：0
|
作者：
Duffy, R [1 ]
Concannon, A [1 ]
Mathewson, A [1 ]
Lane, B [1 ]
机构：
[1] Natl Univ Ireland Univ Coll Cork, Natl Microelect Res Ctr, Cork, Ireland
来源：
MICROELECTRONICS JOURNAL | 2001年 / 32卷 / 01期
关键词：
embedded nonvolatile memory; submicron geometries; scaling issues; short channel effects; disturbs;
D O I：
10.1016/S0026-2692(00)00074-4
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Applications such as systems-on-chip and memory cards require embedded code storage at increasingly small dimensions. In this work a study of scaling embedded EEPROM cells for the integration in deep submicron technologies is undertaken. A well-structured methodology will be proposed and applied to a number of different EEPROM cell types that have been integrated successfully in submicron CMOS processes to date. When scaling embedded nonvolatile memories it is difficult to generate accurate scaling laws or general rules because the performance targets and operating requirements of the memory cells are strongly dependent on the application and process technology in which they are to be integrated. It is possible to generate rules that are application or process technology specific, but it is the aim here to evaluate the scaling of these embedded EEPROMs without a particular application or process technology in mind. (C) 2000 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：35 / 42
页数：8
相关论文
共 50 条
  • [1] Embedded SRAM design in deep deep submicron technologies
    Dehaene, W.
    Cosemans, S.
    Vignon, A.
    Catthoor, F.
    Geens, P.
    ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, : 384 - 391
  • [2] Integration of NiSi SALICIDE for deep submicron CMOS technologies
    Lin, XW
    Ibrahim, N
    Topete, L
    Pramanik, D
    ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS, 1998, 514 : 179 - 184
  • [3] Scaling ISFET Instrumentation with In-Pixel Quantisation to Deep Submicron Technologies
    Moser, Nicolas
    Lande, Tor Sverre
    Georgiou, Pantelis
    PROCEEDINGS OF 2016 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 2016, : 436 - 439
  • [4] A study of integration issues in shallow trench isolation for deep submicron CMOS technologies
    Chatterjee, A
    Mason, M
    Joyner, K
    Rogers, D
    Mercer, D
    Kehne, J
    Esquivel, A
    Mei, P
    Murtaza, S
    Taylor, K
    Ali, I
    Nag, S
    OBrien, S
    Ashburn, S
    Chen, IC
    MICROELECTRONIC DEVICE AND MULTILEVEL INTERCONNECTION TECHNOLOGY II, 1996, 2875 : 39 - 47
  • [5] Mainstream memory technologies in deep submicron
    Natarajan, S
    Alvandpour, A
    MELECON 2004: PROCEEDINGS OF THE 12TH IEEE MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, VOLS 1-3, 2004, : 175 - 178
  • [6] Advanced routing for deep submicron technologies
    Brashears, R
    Kahng, A
    COMPUTER DESIGN, 1997, : 10 - 11
  • [7] SoC integration in deep submicron CMOS
    Rickert, P
    Haroun, B
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 653 - 656
  • [8] Experimental studies on deep submicron CMOS scaling
    Chen, K
    Hu, C
    Fang, P
    Gupta, A
    Lin, MR
    Wollesen, DL
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1998, 13 (07) : 816 - 820
  • [9] Experimental studies on deep submicron CMOS scaling
    IBM Corp, Fishkill, United States
    Semicond Sci Technol, 7 (816-820):
  • [10] Leakage scaling in deep submicron CMOS for SoC
    Lin, YS
    Wu, CC
    Chang, CS
    Yang, RP
    Chen, WM
    Liaw, JJ
    Diaz, CH
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (06) : 1034 - 1041
12345