Wafer-level packaging technology for extended global wiring and inductors

被引：5

作者：

Carchon, G ^{[1
]}

Carbonell, L ^{[1
]}

Jenei, S ^{[1
]}

Van Hove, M ^{[1
]}

Decoutere, S ^{[1
]}

机构：

[1] IMEC, B-3001 Heverlee, Belgium

来源：

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSDERC.2003.1256821

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Wafer level packaging (WLP) technology, originally introduced for thin film redistribution layers, offers novel opportunities for extended global wiring and passives and has been used to integrate transmission lines and state-of-the-art high Q on-chip inductors on top of a five-levels-of-metal (5ML) Cu/oxide back-end of line (BEOL) 20Omegacm silicon process. The transmission lines and inductors are realized above the passivation using thick post-processed dielectric (BCB, epsilon(r)=2.65) and Cu layers. Measurements on the BEOL before and after post-processing show no significant shifts for all 5 metal layers. Post-processed 50Omega transmission lines have losses below-0.1dB/mm@25GHz,- a 1nH inductor has a peak Q-factor of 38 at 4.7GHz with resonance-frequency (F-res) of 29GHz, the Q-factor tops 30 over 2.6-8.6GHz. Patterned polysilicon ground shields further improve the performance: a Q-Jactor increase of 90% was demonstrated at 7GHz for a 2.25nH inductor.

引用

页码：103 / 106

页数：4

共 6 条

[1]

Carchon G, 2001, MICROWAVE J, V44, P96

[2] Multilayer thin-film MCM-D for the integration of high-performance RF and microwave circuits [J].

Carchon, G ;

Vaesen, K ;

Brebels, S ;

De Raedt, W ;

Beyne, E ;

Nauwelaers, B .

IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2001, 24 (03) :510-519

[3]

CARCHON G, 2003, INTEWGRATED PASSIVE

[4] Polarisation-multiplexed and phase-stepped fibre optic shearography using laser wavelength modulation [J].

Groves, RM ;

James, SW ;

Tatam, RP .

INTERFEROMETRY '99: APPLICATIONS, 1999, 3745 :149-157

[5] High Q inductor add-on module in thick Cu/SiLK™ single damascene [J].

Jenei, S ;

Decoutere, S ;

Winderickx, G ;

Struyf, H ;

Tokei, Z ;

Vervoort, I ;

Vos, I ;

Jaenen, P ;

Carbonell, L ;

De Jaeger, B ;

Donaton, RA ;

Vanhaelemeersch, S ;

Maex, K ;

Nauwelaers, B .

PROCEEDINGS OF THE IEEE 2001 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2001, :107-109

[6]

Yue CP, 1997, 1997 SYMPOSIUM ON VLSI CIRCUITS, P85, DOI 10.1109/VLSIC.1997.623819

← 1 →