Design of a High Efficiency DC-DC Buck Converter With Two-Step Digital PWM and Low Power Self-Tracking Zero Current Detector for IoT Applications

被引:54
作者
Kim, Sang-Yun [1 ]
Park, Young-Jun [1 ]
Ali, Imran [1 ]
Truong Thi Kim Nga [1 ]
Ryu, Ho-Cheol [1 ]
Khan, Zaffar Hayat Nawaz [1 ]
Park, Seong-Mun [1 ]
Pu, Young Gun [1 ]
Lee, Minjae [2 ]
Hwang, Keum Cheol [1 ]
Yang, Youngoo [1 ]
Lee, Kang-Yoon [1 ]
机构
[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 440746, South Korea
[2] Gwangju Inst Sci & Technol, Sch Informat & Commun, Gwangju 61005, South Korea
基金
新加坡国家研究基金会;
关键词
Adaptive window analog to digital converter (ADC); dc-dc buck converter; digital compensator; digital pulse width modulation (DPWM); hybrid digital pulse width modulation core; self-tracking zero current detector (ST-ZCD);
D O I
10.1109/TPEL.2017.2688387
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a high efficiency dc-dc buck converter with two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD) is proposed for Internet of Things (IoT) and ultralow power applications. The hybrid DPWM core with high linearity and low power consumption is proposed to implement the high efficiency DPWM dc-dc converter. It is composed of a two-step delay control using the counter and delay line. An adaptive window analog to digital converter is proposed to reduce the output voltage ripple within 20 mV. A dead time generator is implemented with the proposed ST-ZCD to minimize the reverse current. The ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the dc-dc converter. Also, all digital type-III compensator is implemented for the low power and small die area. This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage of 1.5-3 V to generate the output voltage of 1.2 V. The total active area is 500 mu m x 300 mu m. The measured peak efficiency of the DPWM dc-dc buck converter is 91.5% with a quiescent current consuming only 130 mu A.
引用
收藏
页码:1428 / 1439
页数:12
相关论文
共 23 条
[1]  
[Anonymous], 1947, J I ELECT ENG
[2]   20 μA to 100 mA DC-DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS [J].
Bandyopadhyay, Saurav ;
Ramadass, Yogesh K. ;
Chandrakasan, Anantha P. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (12) :2807-2820
[3]  
Cao L., 2012, EETIMES
[4]   Multivariable Control of Single-Inductor Dual-Output Buck Converters [J].
Dasika, Jaya Deepti ;
Bahrani, Behrooz ;
Saeedifard, Maryam ;
Karimi, Alireza ;
Rufer, Alfred .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2014, 29 (04) :2061-2070
[5]  
Gao Y, 2012, PROC IEEE INT SYMP, P99, DOI 10.1109/ISIE.2012.6237066
[6]   A digital CMOS PWCL with fixed-delay rising edge and digital stability control [J].
Jang, Young-Chan ;
Bae, Jun-Hyun ;
Park, Hong-June .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (10) :1063-1067
[7]   Configurable Multimode Digital Control for Light Load DC-DC Converters With Improved Spectrum and Smooth Transition [J].
Kapat, Santanu .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2016, 31 (03) :2680-2688
[8]  
Lan P.-H., 2007, P IEEE AS SOL STAT C, P440
[9]   Scalability of Quasi-Hysteretic FSM-Based Digitally Controlled Single-Inductor Dual-String Buck LED Driver to Multiple Strings [J].
Lee, Albert T. L. ;
Sin, Johnny K. O. ;
Chan, Philip C. H. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2014, 29 (01) :501-513
[10]   A high efficiency dual-mode buck converter IC for portable applications [J].
Liou, Wan-Rone ;
Yeh, Mei-Ling ;
Kuo, Yueh Lung .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2008, 23 (02) :667-677