Comparator offset calibration using unbalanced clocks for high speed and high power efficiency

被引:9
作者
Chiang, Shiuh-hua Wood [1 ]
机构
[1] Brigham Young Univ, Elect & Comp Engn Dept, Provo, UT 84602 USA
关键词
SINGLE-CHANNEL; SAR ADC; CMOS;
D O I
10.1049/el.2016.1157
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel comparator offset calibration using unbalanced clocks is proposed. The new technique avoids loading the comparator core with trimming elements, thus maximising the comparator speed and power efficiency. Simulations show that a comparator utilising the proposed calibration achieves near-native speed and noise performance. It also achieves superior energy-delay-noise product over comparators with conventional calibrations.
引用
收藏
页码:1206 / +
页数:2
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