DC-Link Capacitance Minimization in T-Type Three-Level AC/DC/AC PWM Converters

被引：104

作者：

Alemi, Payam ^{[1
]}

Jeung, Yoon-Cheul ^{[1
]}

Lee, Dong-Choon ^{[1
]}

机构：

[1] Yeungnam Univ, Dept Elect Engn, Kyongsan 712749, South Korea

来源：

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS | 2015年 / 62卷 / 03期

基金：

新加坡国家研究基金会;

关键词：

AC/DC/AC conversion; dc-link capacitance; film capacitor; T-type converter; MULTILEVEL CONVERTERS; INVERTER; DESIGN; STRATEGY;

D O I：

10.1109/TIE.2014.2345354

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a novel control algorithm that minimizes the dc-link capacitance in the T-type three-level back-to-back converter is proposed. For this, the charging and discharging currents through the capacitor should be minimized, which can be achieved by utilizing the power balance of the ac/dc converter. Then, the voltage variation in the dc-link is also decreased, which makes a significant reduction in the size of dc-link capacitors. With this scheme, the electrolytic capacitors can be replaced by film capacitors, which are of higher power density, longer lifetime, and higher reliability. The effectiveness of the proposed strategy has been verified by the simulation and experiment results for a 3-kW T-type three-level ac/dc/ac pulsewidth modulation converter system with a 50-mu F film capacitor in the dc-link.

引用

页码：1382 / 1391

页数：10

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