Jitter in deep submicron CMOS single-ended ring oscillators

被引：4

作者：

Liu, CX ^{[1
]}

McNeill, JA ^{[1
]}

机构：

[1] Worcester Polytech Inst, Dept Elect & Comp Engn, Worcester, MA 01609 USA

来源：

2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/ICASIC.2003.1277310

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 1/f(3) phase noise corner frequency of approximately 1 MHz has been observed in phase noise measurements of single-ended ring oscillators in a 0.18mum CMOS process. Consequently. increased loop bandwidth is necessary for PLLs in a deep submicron CMOS process to minimize jitter contributed by the VCO. As a guide to design. the time domain figure-of-merit kappa is measured as a function of channel width. length. and inverter stage delay.

引用

页码：715 / 718

页数：4

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