Enhancement in IEEE 1500 Standard for at-speed Test and Debug

被引:0
作者
Ali, Ghazanfar [1 ]
Hussini, Fawnizu Azmadi [1 ]
Ali, Noohul Basheer Zain [1 ]
Hamidi, Nor Hisham [1 ]
Adnan, Raja Mahmud [2 ]
机构
[1] Univ Teknol PETRONAS, Ctr Intelligent Signal & Imaging Res CISIR, Elect & Elect Engn Dept, Seri Iskandar, Perak, Malaysia
[2] Intel, Bayan Lepas, Penang, Malaysia
来源
2014 IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE (IEEE DCAS 2014) | 2014年
关键词
IEEE; 1500; Standard; Functional Test; Functional Debug; Software Based Self-Testing (SBST);
D O I
暂无
中图分类号
学科分类号
摘要
IEEE 1500 standard provides the facility to test and debug embedded cores with the use of an on-board or off-board tester. So far all the developments in IEEE 1500 standard are for testing application in the test mode. No development in IEEE 1500 standard is proposed where IEEE 1500-compliant cores can be tested in functional mode of operation. In this paper, an enhancement of the IEEE 1500 standard for functional test and debug is proposed. As a case study, the proposed enhanced IEEE 1500 standard is implemented and validated on a SAYEH processor using embedded Software Based Self-Testing (SBST) technique. The case study demonstrated that the enhancement in IEEE 1500 standard enables it to be used for at-speed test and debug with increased observability.
引用
收藏
页数:4
相关论文
共 11 条
[1]  
[Anonymous], 15002005 IEEE, P1
[2]   Software-based self-testing methodology for processor cores [J].
Chen, L ;
Dey, S .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2001, 20 (03) :369-380
[3]   IEEE Standard 1500 Compatible Delay Test Framework [J].
Chen, Po-Lin ;
Lin, Jhih-Wei ;
Chang, Tsin-Yuan .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (08) :1152-1156
[4]   A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores [J].
Chiu, Geng-Ming ;
Li, James Chien-Mo .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (01) :126-134
[5]  
Higgins M, 2008, IEEE INT SYMP DESIGN, P326
[6]   On-Chip SOC Test Platform Design Based on IEEE 1500 Standard [J].
Lee, Kuen-Jong ;
Hsieh, Tong-Yu ;
Chang, Ching-Yao ;
Hong, Yu-Ting ;
Huang, Wen-Cheng .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (07) :1134-1139
[7]  
Opencore, PROJ SAYEH PROC
[8]  
Sabena D., 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), P25, DOI 10.1109/DFT.2012.6378194
[9]  
Shaheen Ateeq-Ur-Rehman, 2014, INT REV COMPUTERS SO, V9, P832
[10]   At-speed testing of core-based system-on-chip using an embedded micro-tester [J].
Tuna, Matthieu ;
Benabdenbi, Mounir ;
Greiner, Alain .
25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2007, :447-+