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Measurement precision of CD-SEM for 65nm technology node
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Lee JY, 2004, PROC SPIE, V5376, P426, DOI 10.1117/12.534926
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Linton T, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P303, DOI 10.1109/IEDM.2002.1175839
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Modeling line edge roughness effects in sub 100 nanometer gate length devices
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Study of gate line edge roughness effects in 50 nm bulk MOSFET devices
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Metrology of LER: influence of line-edge roughness (LER) on transistor performance
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Characterization of line-edge roughness in resist patterns and estimation of its effect on device performance
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METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVII, PTS 1 AND 2,
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