Design of C-band Frequency Synthesizer for FMCW Transmitter

被引:0
作者
Siddik, Yusuf S. [1 ]
Devi, J. Dhurga [1 ]
Ramakrishna, P. V. [1 ]
机构
[1] Anna Univ, Dept Elect & Commun Engn, CEG Campus, Madras, Tamil Nadu, India
来源
2014 INTERNATIONAL CONFERENCE ON CIRCUITS, COMMUNICATION, CONTROL AND COMPUTING (I4C) | 2014年
关键词
FMCW Frequency Ramp Generator; Linearity; NCO; Phase Locked Loop; Phase noise; verilog-AMS code; TRANSCEIVER;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The present work presents the design of a Phase Locked Loop (PLL) synthesizer for suitable Frequency Modulated Continuous Wave (FMCW) radar applications. The PLL is designed with its loop dynamics selected to exhibit minimum capture transients, fast settling time and low phase noise. High linearity in frequency ramp over a wide operating frequency range coupled with fine frequency steps can be obtained from the proposed PLL synthesizer, a desirable feature for attaining good range resolution and large unambiguous range. The synthesizer is designed using 0.18 mu m UMC technology CMOS process libraries, and the performance results are presented to demonstrate the correct operation of the circuit.
引用
收藏
页码:37 / 40
页数:4
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