A Variable DC Bus Voltage Based Power Hardware-in-the-Loop Emulation of Electric Motors with Wide Variation in Interface Filter Inductance

This paper presents a new scalable power hardware-in-the-loop (PHIL) architecture for emulation of electric motors. It incorporates an additional bidirectional dc-dc converter interface between the emulation and regenerative inverters. The dc-bus for emulation inverter can then be regulated optimally, thus improving its efficiency and reducing harmonic distortion at low speed and light load operation. The counter voltage reference calculation that takes into account wide variation in interface filter inductance due to soft magnetic characteristics of inductor core is also proposed in this paper. A wide range of machine models in abc-domain can then be emulated with just one PHIL test bench. A 2 kW permanent magnet synchronous motor (PMSM) is emulated in this paper and compared with a real motor, to verify feasibility of the proposed method.