Design of a two-bit-per-cell content-addressable memory using single-electron transistors

被引：0

作者：

Degawa, Katsuhiko ^{[1
]}

Aoki, Takafumi

Higuchi, Tatsuo

Inokawa, Hiroshi

Takahashi, Yasuo

机构：

[1] Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 9808579, Japan

[2] Tohoku Inst Technol, Fac Engn, Dept Elect Engn, Sendai, Miyagi 9828577, Japan

[3] NTT Corp, NTT Basic Res Labs, Atsugi, Kanagawa 2430198, Japan

[4] Hokkaido Univ, Grad Sch Informat Sci & Technol, Sapporo, Hokkaido 0600814, Japan

来源：

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING | 2007年 / 13卷 / 03期

关键词：

single-electron transistors; content-addressable memories;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a circuit design of a two-bit-per-cell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETS with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces both the number of transistors and the cell area to 1/3 compared with the conventional CAM architecture.

引用

页码：249 / 266

页数：18

共 14 条

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