Near-threshold Circuit Variability in 14nm FinFETs for Ultra-low power Applications

被引：0

作者：

Balasubramanian, Sriram ^{[1
]}

Pimparkar, Ninad ^{[1
]}

Kushare, Mangesh ^{[1
]}

Mahajan, Vinayak ^{[2
]}

Bansal, Juhi ^{[1
]}

Shimizu, Takashi ^{[2
]}

Joshi, Vivek ^{[1
]}

Qian, Kun ^{[1
]}

Dasgupta, Arunima ^{[2
]}

Chandrasekaran, Karthik ^{[2
]}

Weintraub, Chad ^{[3
]}

Icel, Ali ^{[1
]}

机构：

[1] GLOBALFOUNDRIES, Santa Clara, CA 95054 USA

[2] GLOBALFOUNDRIES, Malta, NY USA

[3] GLOBALFOUNDRIES, Austin, TX USA

来源：

PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016 | 2016年

关键词：

CMOS; variability; delay scaling; Ultra-low power; Near-threshold CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ultra low power (ULP) applications use supply voltage (Vdd) scaling as an effective way of reducing power. However, as Vdd is scaled near the threshold voltage (Vt), increased variability limits the minimum Vdd and power that can be realized. This paper outlines a Veff variability framework to capture the total delay variation seen in digital circuits and describes its applicability for near-threshold delay variability analysis. The low-voltage variability framework has been validated against 14nm-FinFET ring oscillator (RO) measurements.

引用

页码：258 / 262

页数：5

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