Dual port memory based parallel programmable architecture for DSP in FPGA

被引：1

作者：

Zabolotny, Wojciech M. ^{[1
]}

机构：

[1] Warsaw Univ Technol, Inst Elect Syst, PL-00665 Warsaw, Poland

来源：

PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS 2010 | 2010年 / 7745卷

关键词：

FPGA; DSP; parallel processing; dual port memory;

D O I：

10.1117/12.872828

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This document presents a proposal of a new architecture for implementation of Digital Signal Processing (DSP) algorithms in Field-Programmable Gate Array (FPGA). The proposed approach uses the dual port memory for fast exchange of information between the processing units implemented in the FPGA. The special, parametrized scheme of interconnections between processing units has been also proposed, which allows to synthesize DSP system with customized number of processing units. The proposed interconnections scheme provides possibility to quickly transfer the data between processing units, at reasonable consumption of routing resources. The proposed architecture has been tested in simulations, and synthesized for real FPGA chips to verify its correctness.

引用

页数：8