A low cost RSA chip based on CRT

In this paper, the authors present a VLSI design and ASIC implementation of a low cost RSA cryptosystem based on the modified Montgomery algorithm and the Chinese Remainder Theory (CRT), as well as a new scheduling scheme. The CRT technique improves data throughput, and the new scheduling scheme reduces hardware complexity. As a result, a 1024-bit modular exponentiation calculation can be performed in about 1.2 mega cycles, and the core size is less than 54K gates. With 40MHz system clock, a signature rate over 33kbps can be achieved. Using the SMIC 0.25um CMOS process, the clock frequency can be up to 125MHz and in sequence the signature rate to 100kbps.