Variation of threshold voltage in strained Si metal-oxide-semiconductor field-effect transistors induced by non-uniform strain distribution in strained-Si channels on silicon-germanium-on-insulator substrates

The variation of threshold voltage in metal-oxide-semiconductor field-effect-transistors (MOSFETs) fabricated on strained Si on SiGe-on-insulator (SGOI) substrates is evaluated. A large variation of the threshold voltage is observed for MOSFETs on SGOI formed by the conventional Ge condensation method. It is experimentally revealed that the variation of threshold voltage is attributable to the variation of strain in the Si channel layers. This variation is found to be correlated with the variation of the lattice spacing in the SGOI crystal layers, which is caused by non-uniform lattice relaxation in the SGOI layers during the condensation process. It is also found that the variation of the relaxation ratio of SGOI can be significantly suppressed by the two-step oxidation and Ge condensation method.