Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS

被引:3
作者
Lopacinski, L. [1 ]
Hasani, A. [1 ]
Panic, G. [1 ]
Maletic, N. [1 ,2 ]
Schrape, O. [1 ]
Gutierrez, J. [1 ]
Krstic, M. [1 ,3 ]
Grass, E. [1 ,2 ]
机构
[1] IHP Leibniz Inst Innovat Mikroelekt, Frankfurt, Germany
[2] Humboldt Univ, Inst Informat, Berlin, Germany
[3] Univ Potsdam, Potsdam, Germany
来源
2022 JOINT EUROPEAN CONFERENCE ON NETWORKS AND COMMUNICATIONS & 6G SUMMIT (EUCNC/6G SUMMIT) | 2022年
关键词
polar codes; belief propagation; forward error correction; chip layout;
D O I
10.1109/EuCNC/6GSummit54941.2022.9815566
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose pipelining and unrolling schemes for ultra-high speed belief propagation polar decoders. The proof of concept implementation in 28 nm CMOS technology achieves 1380 Gbps of coded throughput with a short polar codeword length of 512 bits, placing it as one of the fastest soft-decision FEC implementations published so far. With a codeword of length 1024 bits, the decoding throughput can be even higher. Moreover, the decoder shows better error correction performance than other ultra-high speed polar decoders published recently. The consumed chip area is 5.98 mm(2), and the chip uses five unrolled iterations with constant quantization of four bits at every processing stage.
引用
收藏
页码:434 / 439
页数:6
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